The present invention relates to a semiconductor device having a complementary MOS transistor and a double-diffused MOS transistor on a single semiconductor substrate, and a method of manufacturing the same.
A semiconductor device having a complementary MOS transistor (to be referred to as a C-MOS hereinafter) and a double-diffused MOS transistor (to be referred to as a D-MOS hereinafter) on a single substrate has been anticipated as a power IC with a high speed logic since a lower power consumption logic circuit can be constituted at the C-MOS and a high output can be obtained from the D-MOS.
FIG. 1 is a sectional view of an example of a conventional semiconductor device which consists of the above-mentioned C-MOS and D-MOS. In FIG. 1, N-type epitaxial silicon layer 2 is formed on P-type silicon substrate 1, and P.sup.+ -type isolation diffusion layer 3 is formed in layer 2 from its surface to substrate 1, so that element regions for C-MOS and D-MOS are isolated. C-MOS 10 and D-MOS 20 are respectively formed in the isolated element regions. Gate electrodes of C-MOS 10 and D-MOS 20 consist of a polycrystalline silicon layer which is doped with high concentration phosphorus to have a low resistance. Reference numeral 4 denotes a field oxide film.
The above conventional semiconductor device is manufactured as shown in FIGS. 2A to 2C.
First, by a process normally performed in manufacturing a bipolar semiconductor device, layer 2 is formed, and then layer 3 is formed to isolate respective element regions. Subsequently , C-MOS 10 and D-MOS 20 are formed in the respective element regions. That is, using the process performed in normal C-MOS processes, P-type well region 11 for an n-channel MOS transistor (to be referred to as an N-MOS hereinafter) is formed in the element region of C-MOS 10. At the same time, P-type well region 21 for withstand voltage compensation is formed in the element region for D-MOS 20. P-type back gate region 22 of D-MOS 20 is formed first, and field oxide film 4 is formed second. Then, after the field oxide film of the element region is removed so as to expose a surface of the epitaxial silicon layer, the exposed surface is thermally oxidized to form gate oxide film 5. Thereafter, polycrystalline silicon layer 6, as a gate electrode material, is deposited on the entire surface.
Then, phosphorus is diffused in high concentration in layer 6 using POCl.sub.3 as a diffusion source, so that layer 6 has a sufficiently low resistance to serve as a gate electrode (FIG. 2A).
Subsequently, layer 6 is patterned to form gate electrodes 12 and 13 of C-MOS 10 and gate electrode 23 of D-MOS (FIG. 2B).
Then, by ion-implanting arsenic, n.sup.+ - type source region 14 and drain region 15 of the N-MOS are formed, and at the same time, n.sup.+ -type source region 24 and n.sup.+ -type drain region 25 of D-MOS 20 are formed. Subsequently, boron is ion-implanted to form p.sup.+ -type source region 16 and drain region 17 of the P-MOS. After CVD-SiO.sub.2 film 7 is deposited as an insulating interlayer, a contact hole is opened, and aluminum is deposited and patterned to form aluminum wiring 8, such as source and drain electrodes of C-MOS 10 and D-MOS 20 (FIG. 2C).
It should be noted that gate electrodes 12, 13, and 23 in the above conventional semiconductor device are all n-type, because they are doped with phosphorus to obtain a low resistance. Therefore, boron is counterdoped in a P-MOS channel region constituting C-MOS 10 to obtain a transistor of a so-called buried channel type for the following reason. That is, since both the channel region of the P-MOS and the gate electrode are n-type, a work function difference between them is too small to invert the channel region, and it is difficult to obtain a threshold voltage of 1 V or less by the P-MOS consisting of a normal gate oxide film. Thus, counter doping is performed to obtain a lower threshold voltage.
In addition, in the manufacture of a conventional semiconductor device, since P-type back gate electrode region 22 of D-MOS 20 is formed before the formation of gate electrode 23, a mask alignment margin between them must be made. That is, as shown in FIG. 3, length c of the back gate region of D-MOS 20 must be longer by length a of the above mask alignment margin than length b obtained when the region is formed by self-alignment. For this reason, an element size is increased to prevent high packing density, and an ON resistance is increased by an elongated amount of the channel region of D-MOS 20. For example, when mask alignment accuracy is within 1 .mu.m, alignment margin a of 2 .mu.m or more must be made for n.sup.+ -type source region 24 to be formed later. Since a diffusion length (b) of region 22 is normally 4 .mu.m, the ON resistance in this case is increased by 75% as compared with the case in which the region is formed by the self-alignment method.
Despite the above disadvantages, the self-alignment method is not used in the formation of region 22 of D-MOS 20 for the following reason.
That is, in order to form region 22 by self-alignment, boron is ion-implanted using electrode 23 as a blocking mask and then diffused and activated by annealing at a high temperature for a long period of time. However, since electrodes 12, 13, and 23 are already doped with high concentration phosphorus, the phosphorus in electrodes 12, 13, and 23 is diffused to reach epitaxial silicon layer 2, if such annealing is performed at a high temperature for a long period of time. For this reason, controllability of gate threshold voltage Vth is significantly degraded in D-MOS 20 and C-MOS 10, and it is particularly impossible to form a MOS transistor.
Another reason why the self-alignment methed is not adopted in the formation of region 22 in D-MOS 20 is that the P-MOS constituting C-MOS 10 must be of a buried channel type for the above reason.
More specifically, like so-called channel-implantation, boron must be counter-doped to form p.sup.+ -type source region 16 and drain region 17 of the P-MOS before polycrystalline silicon layer 6 for gate electrodes 12 and 13 is formed. The term "channel-implementation" means ion-implantation of an impurity in a channel region to control the threshold voltage, because the impurity is segregated into gate oxide film 5 when the film is formed. Accordingly, when the self-alignment method is adopted for formation of region 22, high temperature annealing must be performed after counter doping. Furthermore, since the impurity concentration of layer 2 is lower than that of normal C-MOS 10 with D-MOS 20, to increase a withstand voltage of D-MOS 20, counter-doped boron is diffused deep into layer 2 by the above annealing. As a result, since a p-n junction is formed in a channel region much deeper than that in a normal buried channel type, it is either impossible or very difficult to form the P-MOS.
In addition, due to the above reason, it is difficult for C-MOS 10 to have a satisfactory complementary operation characteristic in a conventional semiconductor device because the P-MOS constituting C-MOS 10 is of a buried channel type.